用于辐射硬化的三级DR-VCO中VCO延迟单元拓扑的研究

K. A. Karthigeyan, P. Chandramani
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引用次数: 4

摘要

采用90nm CMOS工艺设计的基于宽调谐范围延迟单元的3级差分环压控振荡器,工作频率为2.6 GHz,与二极管连接、三极管负载和Maneatis负载延迟单元拓扑相比,具有更好的单事件容错能力。这种拓扑结构可用于PLL和DLL时钟生成应用,以提高LET值在10-50 MeV-cm2/mg之间的辐射容忍度。
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Study of VCO Delay Cell Topologies in a 3-stage DR-VCO for Radiation Hardening
Wide tuning range delay cell based 3-stage differential ring VCO designed using 90nm CMOS process operating at 2.6 GHz frequency shows better single event tolerance compared to diode-connected, triode load and Maneatis load delay cell topologies. This topology can be used in PLL and DLL clock generation applications for improved radiation tolerance for LET values between 10–50 MeV-cm2/mg.
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