26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC

The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SARADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relaxes the noise requirements of the second stage and enhances the overall ADC speed while maintaining excellent power efficiency [1-4]. However, designs reported in [1,2] rely on power-hungry telescopic amplifiers that also limit the available inter-stage residue gain due to low output swing. A lower-power alternative is a dynamic amplifier, which operates as an open-loop time-domain integrator [3,4]. Although time-domain integration provides the benefit of noise filtering, the calibration required to achieve an accurate residue gain increases design complexity and test cost, and limits robustness. We introduce an uncalibrated fully differential ring-amplifier-based 13b 50MS/s rail-to-rail input swing SAR-assisted pipeline ADC with Waiden and Schreier (SNDR) FoMs of 6.9fJ/conversion-step and 174.9dB, respectively. We also present an improved DAC switching technique that further reduces the first DAC energy consumption and also reduces the DAC errors.