用于0.2 /spl mu/m SOI技术的全耗尽蓄积式PMOSFET

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI:10.1109/SOI.1995.526436

C. Raynaud, J. Pelloie, O. Faynot, B. Dunne, J. Hartmann

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引用次数: 1

摘要

SOI技术是低压低功耗应用的一个很有前途的候选者，在这些应用中，部分和完全耗尽的器件都可以用来满足相关要求。完全耗尽器件的一个优点是可以为先进的CMOS工艺保留单个N+栅极工艺。我们在本文中表明，使用N+栅极的累加模式全耗尽PMOSFET可以针对0.2 /spl mu/m SOI CMOS技术进行优化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fully-depleted accumulation-mode PMOSFET for 0.2 /spl mu/m SOI technology

SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 /spl mu/m SOI CMOS technology.

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1995 IEEE International SOI Conference Proceedings

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