Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps

A logic-compatible embedded NAND (eNAND) flash memory based synapse with 3 bit per cell weight storage and 1μA current steps was demonstrated in a standard 65nm CMOS process. The eNAND flash based neuromorphic core consists of 16stack eNAND strings. Each flash cell is composed of 3 transistors (2 PMOS and 1 NMOS) and each string is connected to the main bitline via 2 additional NMOS access transistors. In this work, we realized 3 bit weight based on 1μA current steps using the proposed back-pattern tolerant program-verify scheme. To evaluate the reliability of eNAND Flash based synapses, we measured the temperature dependence, read disturbance, and retention characteristics from a 65nm test chip with 3 bit per cell weight storage and 1μA current steps.