CMOS电路中I/sub DDQ/桥接故障测试的测试生成

1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI:10.1109/TEST.1991.519723

S. Bollinger, S. Midkiff

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引用次数: 32

摘要

本文描述了一种测试生成方法，该方法支持CMOS电路中不受限制桥接故障的显式IDDe测试生成。采用模块化、层次化的方法精确地表示CMOS设计风格的结构并管理复杂性。给出了该方法初步实现的性能结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS

This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.

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1991, Proceedings. International Test Conference

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