VLSI微电路互连线认证的高加速寿命测试方法和程序

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208144

E. Weis, E. Kinsbron, G. Chanoch, M. Snyder

{"title":"VLSI微电路互连线认证的高加速寿命测试方法和程序","authors":"E. Weis, E. Kinsbron, G. Chanoch, M. Snyder","doi":"10.1109/VTEST.1991.208144","DOIUrl":null,"url":null,"abstract":"As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"638 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification\",\"authors\":\"E. Weis, E. Kinsbron, G. Chanoch, M. Snyder\",\"doi\":\"10.1109/VTEST.1991.208144\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<<ETX>>\",\"PeriodicalId\":157539,\"journal\":{\"name\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"volume\":\"638 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1991.208144\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

由于集成电路制造技术的进步，电迁移已经成为硅VLSI电路可靠性的主要问题。本文代表了一种创新的测试方法，可以大大减少金属薄膜的电迁移测试时间，并且可以作为在线过程电迁移监视器实现

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification

As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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