{"title":"电网电压降漏电引起的电路时序脆弱性的统计估计","authors":"I. A. Ferzli, F. Najm","doi":"10.1109/ICICDT.2004.1309896","DOIUrl":null,"url":null,"abstract":"Statistical Vt variations lead to large variations of leakage current, which cause statistical voltage drops on the power grid that can affect Circuit timing. We propose a statistical analysis technique whereby variances of the leakage currents are used to estimate the susceptibility to timing violations due to leakage-induced voltage drops.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop\",\"authors\":\"I. A. Ferzli, F. Najm\",\"doi\":\"10.1109/ICICDT.2004.1309896\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Statistical Vt variations lead to large variations of leakage current, which cause statistical voltage drops on the power grid that can affect Circuit timing. We propose a statistical analysis technique whereby variances of the leakage currents are used to estimate the susceptibility to timing violations due to leakage-induced voltage drops.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309896\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309896","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop
Statistical Vt variations lead to large variations of leakage current, which cause statistical voltage drops on the power grid that can affect Circuit timing. We propose a statistical analysis technique whereby variances of the leakage currents are used to estimate the susceptibility to timing violations due to leakage-induced voltage drops.