Analysis and design of low-power multi-threshold MCML

Multi-threshold MOS current mode logic (MTMCML) is a natural evolution for MCML that offers power saving through supply voltage reduction while retaining the same performance. In this work, analytical formulation based on the BSIM3v3 model is proposed for MTMCML with error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.