用于125+MHz性能(sram)晶圆探测的多层陶瓷(MLC)接口设计

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208145

George M. Belansek, P. Loomis, F. Towler, Charles Warner, D. Wheeler

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摘要

提出了一种采用多层陶瓷(MLC)衬底作为晶圆测试仪接口基础的设计方案。接触225 μ m中心的27*27衬垫矩阵;该设计取代了晶圆探头和测试性能板之间的手工线接口。显著降低了信号串扰和电源噪声。

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A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)

A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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