用于SOI电路的动态体放电技术

J. Kuang, M. J. Saccamango, P. Lu, C. Chuang, F. Assaderaghi
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引用次数: 13

摘要

已有报道(Kuang et al., 1997;Lu et al., 1997)指出,SOI通道电路受到历史效应和不利的初始周期寄生双极电流的影响,这导致电路定时困难,并限制了原始批量电路的直接设计重用。在双轨静态或动态CMOS电路中,SOI器件的本体历史也会导致传输特性不匹配,从而导致速度下降或功能故障。本文描述了一种有效的技术,以减轻初始周期双极电流,同时保持低v /sub /浮体特性时,有关的SOI器件。我们还提出了一种动态体放电技术,以消除交叉耦合SOI CMOS拓扑中的失配问题,可用于各种电路系列,如级联电压开关逻辑,锁存型检测放大器和模拟运算放大器。
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A dynamic body discharge technique for SOI circuit applications
It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.
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