{"title":"一种可扩展且鲁棒的dll轨对轨延迟单元","authors":"Håkan Bengtson, C. Svensson","doi":"10.1109/SOCC.2004.1362378","DOIUrl":null,"url":null,"abstract":"This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"172 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A scalable and robust rail-to-rail delay cell for DLLs\",\"authors\":\"Håkan Bengtson, C. Svensson\",\"doi\":\"10.1109/SOCC.2004.1362378\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.\",\"PeriodicalId\":184894,\"journal\":{\"name\":\"IEEE International SOC Conference, 2004. Proceedings.\",\"volume\":\"172 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International SOC Conference, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2004.1362378\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International SOC Conference, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2004.1362378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A scalable and robust rail-to-rail delay cell for DLLs
This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.
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