双核64b UltraSPARC微处理器实现的深亚微米设计挑战

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309933

T. Takayanagi, J. L. Shin, J. Su, A. Leon

{"title":"双核64b UltraSPARC微处理器实现的深亚微米设计挑战","authors":"T. Takayanagi, J. L. Shin, J. Su, A. Leon","doi":"10.1109/ICICDT.2004.1309933","DOIUrl":null,"url":null,"abstract":"A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"19 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation\",\"authors\":\"T. Takayanagi, J. L. Shin, J. Su, A. Leon\",\"doi\":\"10.1109/ICICDT.2004.1309933\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"19 5\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309933\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

处理器核心最初设计为0.5/spl mu/m Al进程，重新设计为0.13/spl mu/m Cu进程，以创建具有1MB集成L2缓存的双核处理器，为计算密集的服务器应用程序提供高效的性能与功率比。讨论了电路设计挑战，包括负偏置温度不稳定性(NBTI)、泄漏、耦合噪声和模内工艺变化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

自引率

0.00%

发文量