A MIXED FUNCTIONAL/IDDQ TESTING METHODOLOGY FOR CMOS TRANSISTOR FAULTS

A mixed functional/IDDQ testing methodology is presented for detecting transistor faults in CMOS VLSI circuits. A fault preprocessor and a fast switch-level fault simulator have been developed for implementing this testing methodology. The fault preprocessor performs fault generation and collapsing of CMOS transistor faults and identifies those transistor faults that are undetectable by functional testing. Faults that are detectable by functional testing are simulated by the switch-level fault simulator using logic monitoring of the circuit outputs. Faults that are deterministically undetectable by functional testing are considered for detection by monitoring the IDDQ current. These faults are detected if they create conducting transistor paths between VDD and GND, thus elevating IDDQ. By using accurate electrical evaluation techniques of the switch-level circuit state the number of faults that are determined to be detectable by functional testing is increased and the corresponding number of faults requiring IDDQ testing is decreased. This decreases the number of test vectors where IDDQ testing is required and therefore minimizes the total test time.