{"title":"基于多速率ADPLL的毫米波FMCW雷达发射机","authors":"Wanghua Wu, Xuefei Bai, R. Staszewski, J. Long","doi":"10.1109/RFIC.2013.6569535","DOIUrl":null,"url":null,"abstract":"We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A mm-Wave FMCW radar transmitter based on a multirate ADPLL\",\"authors\":\"Wanghua Wu, Xuefei Bai, R. Staszewski, J. Long\",\"doi\":\"10.1109/RFIC.2013.6569535\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.\",\"PeriodicalId\":203521,\"journal\":{\"name\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2013.6569535\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2013.6569535","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A mm-Wave FMCW radar transmitter based on a multirate ADPLL
We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.