{"title":"基于SEC代码的FSM容错体系结构分析与比较","authors":"R. Rochet, R. Leveugle, G. Saucier","doi":"10.1109/DFTVS.1993.595604","DOIUrl":null,"url":null,"abstract":"Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Analysis and comparison of fault tolerant FSM architecture based on SEC codes\",\"authors\":\"R. Rochet, R. Leveugle, G. Saucier\",\"doi\":\"10.1109/DFTVS.1993.595604\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.\",\"PeriodicalId\":213798,\"journal\":{\"name\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1993.595604\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1993.595604","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and comparison of fault tolerant FSM architecture based on SEC codes
Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.
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