Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon
{"title":"spad诱导DCR漂移的应力因素及降解机制的鉴定","authors":"Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon","doi":"10.1109/IIRW56459.2022.10032759","DOIUrl":null,"url":null,"abstract":"The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Identification of stress factors and degradation mechanisms inducing DCR drift in SPADs\",\"authors\":\"Mathieu Sicre, X. Federspiel, D. Roy, Bastien Mamby, C. Coutier, F. Calmon\",\"doi\":\"10.1109/IIRW56459.2022.10032759\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.\",\"PeriodicalId\":446436,\"journal\":{\"name\":\"2022 IEEE International Integrated Reliability Workshop (IIRW)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Integrated Reliability Workshop (IIRW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW56459.2022.10032759\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW56459.2022.10032759","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Identification of stress factors and degradation mechanisms inducing DCR drift in SPADs
The reliability of Single-Photon Avalanche Diodes (SPADs) is addressed by measurement of Dark Count Rate (DCR) drift as a function of stress time (ΔDCR). The degradation mechanisms are analyzed performing stress-conditions at various temperatures, voltages, and irradiances. Measurement and simulation of current are performed to reinforce the degradation assumptions. Potential degradation locations are investigated by comparison of initial and post ageing DCR at different temperatures together with simulations covering defect position and number in the device. Different variations of manufacturing processes are also studied to further confirm defect positions. All the results have allowed identification of the plausible degradation mechanisms, including Hot-Carrier Degradation (HCD) and charge accumulation at the upper interface occurring in SPADs over a wide range of stress conditions.