用于物联网的61 μA/MHz可重构应用专用处理器和片上系统

Y. Huan, Ning Ma, S. Blixt, Z. Zou, Lirong Zheng
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引用次数: 1

摘要

本文提出了一种SoC设计,该设计将通用控制和特定于应用程序的加速结合在可重构的ASIP核心中,用于物联网应用。高度可定制的数据路径和高效的序列控制回路提供了足够的处理能力和可重构性。通过充分利用所提出的架构的数据路径,处理器显着减少了>4倍的代码大小,并在FIR和wheetstone基准测试中提供了比MSP430和Atmega128更优越的性能。在没有额外硬件加速器的情况下,通过优化微指令执行加密算法可以获得10倍以上的加速。在0.18 μm CMOS中制造,我们的SoC的能量效率低至61 μA/MHz,击败了大多数微控制器。
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A 61 μA/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things
This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.
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