千兆级集成(GSI)的SOI MOSFET波动极限

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI:10.1109/SOI.1999.819849

Xinghai Tang, V. De, Lihui Wang, J. Meindl

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引用次数: 5

摘要

利用新颖的三维紧凑物理模型研究了完全耗尽(FD)单门(SG)和双门(DG) SOI mosfet以及部分耗尽(PD) SOI mosfet的内在和外在阈值电压(V/sub /)波动。对于sub-100 nm技术世代，由于内在随机掺杂物放置导致的阈值电压最大偏差可以升级到超过/spl plusmn/100%。在未掺杂的SOI mosfet中探索了更小(<1.5 mV)的固有阈值电压波动。

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SOI MOSFET fluctuation limits on gigascale integration (GSI)

Intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) SOI MOSFETs are investigated using novel 3D compact physical models. Threshold voltage maximum deviations due to intrinsic random dopant placement can escalate to more than /spl plusmn/100% for sub-100 nm technology generations. Much smaller (<1.5 mV) intrinsic threshold voltage fluctuations in undoped SOI MOSFETs are explored.

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1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

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