MOS VLSI中操作诱发故障的分析与测试

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208148

R. Rajsuman, A. Jayasumana, Y. Malaiya, Juney Park

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引用次数: 4

摘要

讨论了CMOS电路中的操作诱发故障。指出了这些故障对高密度小几何电路的意义。为了建模的目的，这些断层的影响与经典断层模型相关联。提出了一个包含这些故障的电导故障模型。提出了一种基于电源电流测量的故障检测方案。本文还概述了为这些故障生成测试模式的方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An analysis and testing of operation induced faults in MOS VLSI

The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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