时钟发生器锁相环在TID效应下的性能分析

A. Rossetto, G. Wirth, Ricardo Vanni Dallasen
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引用次数: 3

摘要

锁相环作为频率合成器被广泛应用于时钟信号的产生。然而,在航空航天环境中,由于辐射暴露,锁相环的性能会下降,从而导致其组件参数的退化。因此,本文提出了时钟发生器锁相环在TID效应下的性能分析。分析了不同累积剂量下的输出频率、功耗和控制电压变化,并与正常工作结果进行了比较,证明了性能的下降。锁相环功能失效也进行了观察和讨论。采用0.35μm CMOS工艺设计了该电路,并利用HSPICE模拟器进行了仿真。
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Performance analysis of a clock generator PLL under TID effects
Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption and control voltage variations are analyzed for different accumulated doses and compared with normal operating results, evidencing the performance degradation. PLL functional failures were also observed and discussed. The circuit was designed in a 0.35μm CMOS process and the simulations were performed using HSPICE simulator.
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