采用0.25 /spl mu/m SOI CMOS技术，具有50 MHz采样率的低功耗/spl Sigma//spl Delta/模数调制器

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI:10.1109/SOI.1999.819835

A. Swaminathan, N. Fong, P. Lauzon, Hong-Kui Yang, M. Maliepaard, C. Plett, M. Snelgrove

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引用次数: 0

摘要

二阶双采样模数/spl Sigma//spl Delta/调制器在0.25 /spl mu/m全耗尽绝缘体上硅(FDSOI) CMOS工艺中实现。与传统的块体CMOS相比，FDSOI具有更好的亚阈值摆幅和更少的短通道效应，因此可以降低阈值电压，从而降低低功耗应用的电源电压。

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A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology

A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.

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1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

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