基于仿真的时间抽象模型硬件验证

A. Kamkin
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引用次数: 4

摘要

基于仿真的验证是一种广泛采用的确保硬件设计功能正确性的方法[1,2]。它通常是通过与独立创建的参考模型共同模拟正在验证的设计并检查其反应的一致性来完成的。为了减少验证费用,通常使用抽象模型(它们更简单,更不容易出错,并且更易于重用)。设计时序(将操作分解为微操作并对这些微操作进行调度)是抽象的主要对象。然而,在使用时间抽象参考模型进行基于仿真的验证时存在一些问题。本文讨论了其中的一些问题,并提出了解决这些问题的简单实用的方法。
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Simulation-based hardware verification with time-abstract models
Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design timing (decomposition of operations into micro-operations and scheduling of those micro-operations) is the main object for abstraction. However, there are several problems in using time-abstract reference models for simulation-based verification. The paper discusses some of the problems and suggests simple, practice-oriented techniques to solve them.
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