逻辑测试的漏洞:混合信号ASIC

R. Prilik, J. Vanhorn, D. Leet
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引用次数: 13

摘要

作者调查了可能限制混合信号的测试相关漏洞。所有的漏洞都与三个基本环境特征中的一个或多个有关。首先,混合信号ASIC(专用集成电路)组件缺乏旧组件/卡测试级别的可控性和可观察性。其次,在设计的逻辑和模拟部分之间有更紧密的交互。第三,设计和产品生命周期被压缩到现有卡和组件测试方法和过程不再满足需求的程度。他指出,导致混合信号测试方法显著改进的关键发展是最新一代基于混合信号、数字信号处理器(DSP)的测试/工作站。特别重要的是这些系统提供的计算机自动化设计软件,它可以为测试设计和测试生成开发建立一个更好的环境。
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The loophole in logic test: mixed signal ASIC
The author surveys test-related loopholes that could limit mixed signals. All the loopholes are related to one or more of three fundamental environmental characteristics. First, mixed-signal ASIC (application-specific integrated circuit) components lack the controllability and observability seen at old component/card test levels. Second, there is much closer interaction between the logic and analog portions of a design. Third, design and product life cycles are being compressed to the point where existing card and component test methodologies and processes no longer meet requirements. He shows that the key development that will lead to significant improvements in mixed signal test methodologies is the most recent generation of mixed-signal, digital signal processor (DSP)-based tester/work stations. Particularly important is computer-automated design software that these systems provide, which may establish a better environment for design-for-test and test generation development.<>
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