M. Claus, D. Teich, S. Mothes, G. Seifert, M. Schroter
{"title":"非规则缺陷模式cntfet的多尺度建模","authors":"M. Claus, D. Teich, S. Mothes, G. Seifert, M. Schroter","doi":"10.1109/IWCE.2015.7301947","DOIUrl":null,"url":null,"abstract":"An important consideration in the design and reliability of circuits is the role of defects, impurities, and parameter fluctuations in affecting the transistor characteristics. Here, the impact of vacancies on CNTFET characteristics is studied by means of a multi-scale modeling and simulation framework. Very recently, defect densities of 0:02% up to 0:2% have been reported for different CNT samples. Therefore and in contrast to other simulation studies [1] at the device level, the impact of defects beyond the single defect limit is analyzed. Our atomistic simulation results suggest the developed defect model at the device level to be a reasonable approach. In addition, it has been shown that in contrast to a single defect, multiple defects lead to a larger variability of the device performance.","PeriodicalId":165023,"journal":{"name":"2015 International Workshop on Computational Electronics (IWCE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Multiscale-modeling of CNTFETs with non-regular defect pattern\",\"authors\":\"M. Claus, D. Teich, S. Mothes, G. Seifert, M. Schroter\",\"doi\":\"10.1109/IWCE.2015.7301947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An important consideration in the design and reliability of circuits is the role of defects, impurities, and parameter fluctuations in affecting the transistor characteristics. Here, the impact of vacancies on CNTFET characteristics is studied by means of a multi-scale modeling and simulation framework. Very recently, defect densities of 0:02% up to 0:2% have been reported for different CNT samples. Therefore and in contrast to other simulation studies [1] at the device level, the impact of defects beyond the single defect limit is analyzed. Our atomistic simulation results suggest the developed defect model at the device level to be a reasonable approach. In addition, it has been shown that in contrast to a single defect, multiple defects lead to a larger variability of the device performance.\",\"PeriodicalId\":165023,\"journal\":{\"name\":\"2015 International Workshop on Computational Electronics (IWCE)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Workshop on Computational Electronics (IWCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWCE.2015.7301947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Workshop on Computational Electronics (IWCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWCE.2015.7301947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiscale-modeling of CNTFETs with non-regular defect pattern
An important consideration in the design and reliability of circuits is the role of defects, impurities, and parameter fluctuations in affecting the transistor characteristics. Here, the impact of vacancies on CNTFET characteristics is studied by means of a multi-scale modeling and simulation framework. Very recently, defect densities of 0:02% up to 0:2% have been reported for different CNT samples. Therefore and in contrast to other simulation studies [1] at the device level, the impact of defects beyond the single defect limit is analyzed. Our atomistic simulation results suggest the developed defect model at the device level to be a reasonable approach. In addition, it has been shown that in contrast to a single defect, multiple defects lead to a larger variability of the device performance.