一种用于超高密度dram的地址屏蔽并行测试

1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI:10.1109/TEST.1991.519718

Y. Morooka, S. Mori, H. Miyamoto, M. Yamada

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引用次数: 9

摘要

本文介绍了一种适用于超高密度dram的新型存储阵列结构及其测试方法——列地址可掩码并行测试(CMT)结构。为了在最小的面积损失下实现有效的并行测试，我们采用了列地址掩蔽技术。CMT体系结构使得处理各种测试模式和在并行测试操作期间快速搜索失败地址成为可能。在实验性64m位DRAM中，测试时间已减少到V16K，面积损失小于0.1%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS

This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.

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