15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<;10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.