PMOS接触电阻解决方案兼容CMOS集成7纳米节点及以上

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2016-04-25 DOI:10.1109/VLSI-TSA.2016.7480531

C. Ni, Y. Huang, S. Jun, S. Sun, A. Vyas, F. Khaja, K. V. Rao, S. Sharma, N. Breil, M. Jin, C. Lazik, A. Mayur, J. Gelatos, H. Chung, R. Hung, M. Chudzik, N. Yoshida, N. Kim

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引用次数: 7

摘要

本文提出了一种改善PMOS接触电阻率(pc)的策略，即形成与Ti/Si(Ge)系统和CMOS集成流程兼容的富锗接触界面。短脉冲(nsec)激光退火和预清洁期间的进一步处理可以有效地使Ge向SiGe表面偏析，从而提高PMOS的ρc。随着Ge%从45%增加到100%，由于带隙调制和首选费米级钉住，pc提高了三倍，从1.28 e-8到2.8e-9 Ωcm2。最后，我们提出了一个cmos集成兼容的触点流程，解决了PMOS和NMOS触点的ρc优化问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

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2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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