Investigation of nano interconnects for an early experimental assessment of future interconnect challenges

The investigation of interconnects with CDs of future technology nodes is limited to direct writing techniques for pattern definition, as next generation lithography is still under investigation. To by-pass the throughput limitations of direct writing, allowing the fabrication of only a limited number of test structures for process adaptations and electrical characterization, alternative approaches were developed. Standard stepper manufacturing lithography was used in combination with additional process tricks to fabricate a large number of test structures across the wafers with CDs down to 20nm, however, at the expense of a relaxed pitch. For a study of the scaling limits of copper damascene and subtractive aluminium metallization, a removable spacer technique and a hard mask trim were developed, respectively. Thus damascene trenches and RIE-masks with deep sub-100nm CDs could be prepared. The electrical characterization of Cu nano interconnects shows that the ITRS requirement for the conductor resistivity will not be met, not even with cooling, in future technology generations. The ITRS red brick wall for barrier films, however, is getting cracks. Barrier functionality with film thicknesses below end-of-roadmap thickness requirements was demonstrated with excellent barrier integrity regarding line-to-line leakage after anneals and after excessive BTS tests. First results on electromigration behaviour of Cu nano interconnects are also encouraging. Results on Al are underway.