S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan
{"title":"Fast/sub 14/ Technology:用于多千兆赫数字逻辑自动化的设计技术","authors":"S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan","doi":"10.1109/ICICDT.2004.1309937","DOIUrl":null,"url":null,"abstract":"Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to \"Fast Silicon Technology\"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic\",\"authors\":\"S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan\",\"doi\":\"10.1109/ICICDT.2004.1309937\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to \\\"Fast Silicon Technology\\\"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309937\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309937","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic
Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to "Fast Silicon Technology"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.