A new method for calculating one-dimensional process margin in consideration of process variations

Yield and device characteristics in VLSI become more sensitive to process variations with finer patterns and enlargement of wafer size. Thus, process integration should take account of the inter- and intra-wafer process variations for elimination of yield loss. However, it is difficult to perform experiments which cover possible process variations because of cost and time. In this paper, we describe a new method for calculating a process margin for processes such as etching and deposition with consideration of process variations using the Monte Carlo method.