{"title":"相变记忆细胞的等离子损伤分析","authors":"F. Pellizzer, A. Spandre, S. Alba, A. Pirovano","doi":"10.1109/ICICDT.2004.1309950","DOIUrl":null,"url":null,"abstract":"Phase change memories based on chalcogenide materials are being studied as an alternative for nonvolatile information storage, because they can become attractive for technology nodes beyond 65 nm due to their intrinsic scalability In this paper we propose a first analysis of plasma damage of phase memory cells, starting from the basic electrical characteristics of storage elements and then including the effects of different selecting devices. Taking into account the architecture of phase change arrays, we will evaluate typical etching conditions and try to understand any possible impact on cell parameters and performances. Finally we will show some electrical results on real devices, integrated in a standard CMOS process in 0.18 /spl mu/m technology.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analysis of plasma damage on phase change memory cells\",\"authors\":\"F. Pellizzer, A. Spandre, S. Alba, A. Pirovano\",\"doi\":\"10.1109/ICICDT.2004.1309950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Phase change memories based on chalcogenide materials are being studied as an alternative for nonvolatile information storage, because they can become attractive for technology nodes beyond 65 nm due to their intrinsic scalability In this paper we propose a first analysis of plasma damage of phase memory cells, starting from the basic electrical characteristics of storage elements and then including the effects of different selecting devices. Taking into account the architecture of phase change arrays, we will evaluate typical etching conditions and try to understand any possible impact on cell parameters and performances. Finally we will show some electrical results on real devices, integrated in a standard CMOS process in 0.18 /spl mu/m technology.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of plasma damage on phase change memory cells
Phase change memories based on chalcogenide materials are being studied as an alternative for nonvolatile information storage, because they can become attractive for technology nodes beyond 65 nm due to their intrinsic scalability In this paper we propose a first analysis of plasma damage of phase memory cells, starting from the basic electrical characteristics of storage elements and then including the effects of different selecting devices. Taking into account the architecture of phase change arrays, we will evaluate typical etching conditions and try to understand any possible impact on cell parameters and performances. Finally we will show some electrical results on real devices, integrated in a standard CMOS process in 0.18 /spl mu/m technology.