The promise and implementation of three dimensional integration

In many ways, three dimensional integration presents itself as a logical extension of planar monolithic integration - integration of additional function on the same die. Notwithstanding the remarkable advances in scaling we have witnessed over the last several decades, basic material limitations and lithography have slowed this trend down and the benefits of node to node migration need to be weighed against both technology development costs and complexity as well as the cost of design migration. Another consideration is die size which for high end applications such as high performance processors continues to increase well beyond the sweet spot dictated by yieldability, driven primarily by multiples cores and on-chip memory. Furthermore in such large die, long electrical paths cause significant delay and power draws. To address these limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way we design an SOC or ASIC today. This talk examines at the technology as it stands toady and the challenges going forward. These challenges include the development of fine pitch vertical interconnects and the degrees of integration they would permit. We will focus on the integration of three dimensional memory as the prototypical example of three dimensional integration and describe how these challenges are being met.