A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI

Multi-port Static Random Access Memories (SRAM) are essential for shared data structures, especially in distributed, multi-core and multi-processing computing systems. This paper introduces an elementary multi-port memory design which can perform either dual-read or a single-write operation (2R/1W) by efficiently combining the 6 Transistor (6T) single-port SRAM (SP-SRAM). This new architecture offers a solution to the existing 8T dual-port (DP) cell problems including read-write stability issues. The design has been evaluated by comparing with the conventional solutions, in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A 2048 words, 64 bit memory shows 31% improvement in performance, 31% reduced area and 19% lesser power consumption than the conventional 8T dual-port SRAM (DP-SRAM). In addition, the proposed design is scalable to large memory capacities which cannot be generated directly using the available dual-port memory compilers.