{"title":"研究了0.13µm CMOS技术的MOS晶体管特性及其等离子体充电退化对测试结构布局的影响","authors":"Andreas Martin, R. Vollertsen, H. Reisinger","doi":"10.1109/IIRW.2010.5706488","DOIUrl":null,"url":null,"abstract":"The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology\",\"authors\":\"Andreas Martin, R. Vollertsen, H. Reisinger\",\"doi\":\"10.1109/IIRW.2010.5706488\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.\",\"PeriodicalId\":332664,\"journal\":{\"name\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"150 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2010.5706488\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2010.5706488","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology
The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.
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