Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique

In this paper, a new write assist technique is proposed to improve the write characteristics of 1T-1MTJ STT-RAM bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write `1' operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared to the boosted wordline technique. In addition, the proposed write assist technique leads to 12% and 48% reduction in the access transistor width compared with boosted wordline and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with boosted wordline and balanced write techniques, respectively.