一种90纳米CMOS谐波抑制宽带倍频器

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377875

Bo-Yu Chen, Yuan-Hung Hsiao, Huei Wang

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引用次数: 4

摘要

本文提出了一种采用90纳米CMOS工艺的宽带倍频器。平衡倍频器采用C类偏置级联码拓扑，最大限度地提高了二次谐波的产生。级联码结构内部集成了椭圆低通滤波器，抑制四次谐波和高次谐波功率。该倍频器的3db带宽为42 ~ 90ghz，在5dbm输入驱动下，转换损耗为8 ~ 11db。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A broadband doubler with harmonic rejection in 90nm CMOS

In this paper, we present a broadband frequency doubler with harmonic rejection using 90nm CMOS process. The balanced frequency doubler adopts cascode topology with class C bias to maximize second order harmonic generation. An elliptic low pass filter is integrated inside the cascode structure to suppress the fourth and higher order harmonic power. The 3-dB bandwidth of this frequency doubler is from 42 to 90 GHz with 8 to 11 dB conversion loss under 5-dBm input drive.

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2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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