26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Recently reported high-speed ADCs have mostly taken advantage of time-interleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases, the power consumption of the front-end flash ADC becomes significant, which reduces the efficiency. In addition, if the target speed is higher than the frequency achievable by a single flash ADC, the FATI SAR ADC should be time-interleaved with multiple flash ADCs. The timing skew calibration scheme reported in [2] cannot be applied in this case. Considering these issues, this work introduces an advanced FATI SAR ADC with a folding-flash (F-flash) ADC that reduces the power burden placed upon a flash ADC. In addition, 2× time interleaving is applied in an effort to lower the conversion rate of the flash ADC (time-interleaved FATI SAR ADC). The offset and timing skew of each channel are calibrated in the background.