自检验与在线检测的自宇称组合电路设计

E. Sogomonyan, M. Gössel
{"title":"自检验与在线检测的自宇称组合电路设计","authors":"E. Sogomonyan, M. Gössel","doi":"10.1109/DFTVS.1993.595814","DOIUrl":null,"url":null,"abstract":"It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design of self-parity combinational circuits for self-testing and on-line detection\",\"authors\":\"E. Sogomonyan, M. Gössel\",\"doi\":\"10.1109/DFTVS.1993.595814\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency.\",\"PeriodicalId\":213798,\"journal\":{\"name\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1993.595814\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1993.595814","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

证明了任意n元布尔函数可以系统地实现为自测试组合电路。这是通过使用奇偶校验位和被监视电路的选定部分的一个或多个复制来实现的。因此,聚会位和功能位是联合设计的,而不是分开设计的。这种电路称为自奇偶电路。与奇偶预测函数的单独实现相比,可以显著降低硬件成本。该电路可用于测试模式和正常工作模式,用于在线故障检测。在正常的在线操作中,检测到故障可能会有一定的延迟。
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Design of self-parity combinational circuits for self-testing and on-line detection
It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency.
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