Clock skew determination from parameter variations at chip and wafer level

Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions at chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42 ps for a 0.25 /spl mu/m process and a metal-3 H-clock tree.