{"title":"VLSI测试系统中高速复用器与解复用器集成的若干问题","authors":"M. Chowanetz, C. Kuntzsch, W. Wolz","doi":"10.1109/VTEST.1991.208142","DOIUrl":null,"url":null,"abstract":"The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems\",\"authors\":\"M. Chowanetz, C. Kuntzsch, W. Wolz\",\"doi\":\"10.1109/VTEST.1991.208142\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<<ETX>>\",\"PeriodicalId\":157539,\"journal\":{\"name\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1991.208142\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208142","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems
The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<>
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