Intel 10+制程上高密度金属-绝缘体-金属电容器的可靠性特性

Cheyun Lin, U. Avci, M. Blount, R. Grover, Jeffery Hicks, R. Kasim, A. Kundu, C. Pelto, C. Ryder, A. Schmitz, K. Sethi, D. Seghete, D. Towner, A. Welsh, J. Weber, C. Auth
{"title":"Intel 10+制程上高密度金属-绝缘体-金属电容器的可靠性特性","authors":"Cheyun Lin, U. Avci, M. Blount, R. Grover, Jeffery Hicks, R. Kasim, A. Kundu, C. Pelto, C. Ryder, A. Schmitz, K. Sethi, D. Seghete, D. Towner, A. Welsh, J. Weber, C. Auth","doi":"10.1109/irps45951.2020.9128312","DOIUrl":null,"url":null,"abstract":"We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO<inf>2</inf>-Al<inf>2</inf>O<inf>3</inf> and HfO<inf>2</inf>-ZrO<inf>2</inf> high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm<sup>2</sup> and 52 fF/μm<sup>2</sup> that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO<inf>2</inf>-ZrO<inf>2</inf> capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm<sup>2</sup> with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process\",\"authors\":\"Cheyun Lin, U. Avci, M. Blount, R. Grover, Jeffery Hicks, R. Kasim, A. Kundu, C. Pelto, C. Ryder, A. Schmitz, K. Sethi, D. Seghete, D. Towner, A. Welsh, J. Weber, C. Auth\",\"doi\":\"10.1109/irps45951.2020.9128312\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO<inf>2</inf>-Al<inf>2</inf>O<inf>3</inf> and HfO<inf>2</inf>-ZrO<inf>2</inf> high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm<sup>2</sup> and 52 fF/μm<sup>2</sup> that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO<inf>2</inf>-ZrO<inf>2</inf> capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm<sup>2</sup> with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.\",\"PeriodicalId\":116002,\"journal\":{\"name\":\"2020 IEEE International Reliability Physics Symposium (IRPS)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Reliability Physics Symposium (IRPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/irps45951.2020.9128312\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/irps45951.2020.9128312","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

我们提出了一种高密度MIM去耦电容器,通过提供强大的片上电源降低,可以提高微处理器的性能。采用ald沉积HfO2-Al2O3和HfO2-ZrO2高k介电体和PVD TiN电极制备了MIM介电体。我们实现了37 fF/μm2和52 fF/μm2的单MIM-cap密度,满足1.98 V和1.26 V使用条件下的可靠性要求。HfO2-ZrO2电容器的可靠性显示出最小的电压极性依赖性,这使得使用多板mim帽可以增加电容密度。我们在四板结构下实现了141 fF/μm2的电容密度,比英特尔14nm工艺的电容密度提高了3.5倍。此外,该堆栈还满足环境压力测试。这种MIM- cap改善了片上功率传输网络,导致微处理器的最大频率增加,现在正在批量出货。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process
We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO2-Al2O3 and HfO2-ZrO2 high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm2 and 52 fF/μm2 that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO2-ZrO2 capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm2 with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures Ruggedness of SiC devices under extreme conditions Gate-Oxide Trapping Enabled Synaptic Logic Transistor Threshold Voltage Shift in a-Si:H Thin film Transistors under ESD stress Conditions Sub-nanosecond Reverse Recovery Measurement for ESD Devices
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1