H. Koike, T. Tanigawa, Toshinari Watanabe, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Yoshiduka, Yitao Ma, H. Honjo, K. Nishioka, S. Miura, H. Inoue, S. Ikeda, T. Endoh
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Review of STT-MRAM circuit design strategies, and a 40-nm 1T-1MTJ 128Mb STT-MRAM design practice
STT-MRAM is now an essential component for future low power consumption electronics. Recently, a number of STT-MRAM developments have been successively disclosed by major LSI vendors [1] –[9], and some of them announced that risk mass-production of STT-MRAM had started. This invited paper reviews, in this opportunity, STT-MRAM circuit design strategies, which cover memory cell design, sense amplifier (S/A) and reference generator (Refgen), and array architecture. Furthermore, as one example of STT-MRAM design, a 128Mb STT-MRAM chip using 40-nm standard CMOS and 3X-nm MTJ technology will be presented [10].
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