用于ASIC和处理器芯片的良率模型

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595739

C. Stapper, J. Patrick, R. Rosner

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引用次数: 11

摘要

基于芯片面积的良率模型不足以模拟CMOS专用集成电路和处理器芯片的良率。基于电路数量的模型给出了更准确的结果。用dram测量的缺陷学习曲线已经成功地用于预测各种芯片的良率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Yield model for ASIC and processor chips

Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips.

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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