{"title":"基于28nm FPGA的后端缺陷定位","authors":"Jack Yi Jie Ng, Liew Chiun Ning, Khoo Khai Ling","doi":"10.1109/IPFA.2014.6898156","DOIUrl":null,"url":null,"abstract":"This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Back-end defect localization for 28nm FPGA\",\"authors\":\"Jack Yi Jie Ng, Liew Chiun Ning, Khoo Khai Ling\",\"doi\":\"10.1109/IPFA.2014.6898156\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.\",\"PeriodicalId\":409316,\"journal\":{\"name\":\"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2014.6898156\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2014.6898156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了基于28nm现场可编程逻辑阵列(FPGA)体硅技术的两个案例，重点介绍了利用本地软件(Interconnect Test Generation, ITG)调试器和Functional Interface)定位后端互连和金属化缺陷的新方法，然后进行了广泛的布局研究、可疑缺陷节点识别、并行研磨和扫描发射显微镜(SEM)检查。
This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
