Quantile Based Statistical Failure Analysis for Wafer Level Test Comparison

In semiconductor manufacturing or testing, when changing the items such as parts, materials or equipment, many engineers use the equivalence test to hedge the risk of new process. Equivalence Test Procedure (ETP) uses a modified algorithm of Cohen's d and F-ratio for comparing two test samples when it evaluates the statistical allowance in the second stage. These logics are estimated under the assumption of normality for the underlying population. However, there are many wafer level test items such as Fail Bit Count (FBC) where their populations are non-normal distribution. Because the standard deviation in the two algorithms is over-estimated in wafer level test distribution, the two algorithms fail to represent the size of difference for the two samples exactly. Therefore, we introduce quantile comparison equivalence criteria (QCEC) which is robust to overall data distribution and outlier-free. To instruct engineers about the change cause of the data distribution, we create new statistics called ‘Center or Dispersion’ (CoD) that distinguish between center difference and dispersion difference. For practical application, we conduct the case study on Dynamic Random Access Memory (DRAM) FBC data. For wafer level test 199 items, it is found that the QCEC's accuracy improves by 20% compared to the accuracy of Cohen's d. It also shows a 75% improvement over the accuracy of the F-ratio.