Choice of Gate Insulator for Effective Gate Electrostatics in Double Gate Nanoscale Mosfet

A numerical model using self consistent Poisson's equation solver is presented to elucidate the potential profile and current-voltage characteristics of double gate nanoMOSFET using 32nm technology. Here we have explored the performance of the nanodevice with different dielectric layers. The focus of this work is to identify the type of gate dielectric material which is capable enough to control the electrostatics across the channel through gate bias and reduce the tunneling current. We find that $\mathrm {T}\mathrm {i}\mathrm {O}_{2}$ layer having k=80 produces higher tunneling current through gate leakage although it exhibited stronger gate control on the channel conduction. A combination of $\mathrm {T}\mathrm {i}\mathrm {O}_{2}$ and $\mathrm {S}\mathrm {i}\mathrm {O}_{2}$ dielectric layers is proposed to mitigate tunnelling in these devices and improve its performance.