Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, S. Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, H. Park, Dong-Hun Kwak, Sangwon Park, Seok-Min Yoon, Wook-Ghee Hahn, J. Ryu, Sang-Won Shim, Kyung-Tae Kang, Sungsoo Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, O. Kwon, Ji-Sang Lee, Moosung Kim, Sanghoon Joo, J. Jang, Sang-Won Hwang, D. Byeon, Hyang-Ja Yang, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi
{"title":"7.2 128Gb b/cell V-NAND闪存，I/O速率为1Gb/s","authors":"Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, S. Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, H. Park, Dong-Hun Kwak, Sangwon Park, Seok-Min Yoon, Wook-Ghee Hahn, J. Ryu, Sang-Won Shim, Kyung-Tae Kang, Sungsoo Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, O. Kwon, Ji-Sang Lee, Moosung Kim, Sanghoon Joo, J. Jang, Sang-Won Hwang, D. Byeon, Hyang-Ja Yang, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi","doi":"10.1109/ISSCC.2015.7062960","DOIUrl":null,"url":null,"abstract":"Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"79","resultStr":"{\"title\":\"7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate\",\"authors\":\"Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, S. Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, H. Park, Dong-Hun Kwak, Sangwon Park, Seok-Min Yoon, Wook-Ghee Hahn, J. Ryu, Sang-Won Shim, Kyung-Tae Kang, Sungsoo Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, O. Kwon, Ji-Sang Lee, Moosung Kim, Sanghoon Joo, J. Jang, Sang-Won Hwang, D. Byeon, Hyang-Ja Yang, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi\",\"doi\":\"10.1109/ISSCC.2015.7062960\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].\",\"PeriodicalId\":188403,\"journal\":{\"name\":\"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"79\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2015.7062960\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2015.7062960","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
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