Design solutions for preventing process induced ESD damage during manufacturing of interconnects

ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS [1]. Little is known however on the impact of simple wafer cleaning/spraying as used frequently during the wafer manufacturing itself. In many cases these processes do include high risks of generating electrostatic charge; subsequent discharge into devices and can easily induce ESD-like events internally in the interconnect circuitry of a device. In this paper, charging induced damage (CID) into common metal interconnect is reported. The damage is caused by the build up of charges on a resist surface during a water rinsing step. This charging is inducing a mirror charge on the interconnect circuitry and results in a discharge through the inter metal dielectric layer (IMD) towards a grounded structure. This CID can lead to direct severe yield loss. In milder cases the damage is difficult to detect but is proven to result in reliability issues. The charging has been detected, measured and evaluated with the help of a non contact surface potential measurement. The phenomena has been characterized and quantified. This paper is describing the occurrence of the failures, the design of the test structures, the measurement results. This work is concluding on how a design can be made safe from ESDFOS during processing by applying the popper layout rules.