{"title":"基于dl的电子束系统的三维NAND垂直通道缺陷检测和分类解决方案:DI:缺陷检测和减少","authors":"Cheng Hung Wu, Yen-Chun Chuan Sun, Rishabh Kushwaha, Piyush Bajpai, Shao Chang Cheng","doi":"10.1109/asmc54647.2022.9792511","DOIUrl":null,"url":null,"abstract":"With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at ~6 μm depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with >90% purity by each VC row.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"3D NAND vertical channel defect inspection and classification solution on a DL-based e-beam system : DI : Defect Inspection and Reduction\",\"authors\":\"Cheng Hung Wu, Yen-Chun Chuan Sun, Rishabh Kushwaha, Piyush Bajpai, Shao Chang Cheng\",\"doi\":\"10.1109/asmc54647.2022.9792511\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at ~6 μm depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with >90% purity by each VC row.\",\"PeriodicalId\":436890,\"journal\":{\"name\":\"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"122 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/asmc54647.2022.9792511\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asmc54647.2022.9792511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D NAND vertical channel defect inspection and classification solution on a DL-based e-beam system : DI : Defect Inspection and Reduction
With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at ~6 μm depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with >90% purity by each VC row.