HF mismatch characterization and modeling of bipolar transistors for RFIC design

This paper presents a methodology to characterize and model BJT's mismatch behavior for RFIC design. A measurement technique based on the conventional S-parameter measurement is developed to measure the mismatch behavior at high frequencies (HFs). First, besides the typical de-embedding, the bondpad mismatch is subtracted statistically from the capacitance mismatch measurement. Second, a semi-empirical methodology using physical parameters, such as window CD and vertical doping, is developed to model the measured AC mismatch behavior for transistors of different size. Finally, a systematic procedure is proposed to extract the mismatch parameters, which can be used in the SPICE Monte-Carlo mismatch simulation. The proposed mismatch modeling methodology is validated on an industrial 0.35μm RF BiCMOS process. The proposed model fits the mismatch characteristics of the key AC parameters, such as CBE, CBC, and fT at different current densities. The model also scales well with geometry for the transistors with sizes useful for RFIC application.